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single chip processing for ccd monochrome camera description the cxA1310AQ is designed to perform the basic signal processing in ccd monochrome cameras with a single chip. this bipolar lc is most suitable for compact usage and low power consumption. features processing from ccd output to 75 video output with a single chip wide variable agc (4 to 32db typ.) built-in operational amplifier for agc loop 75 line capacitance minimized using sag compen- sation function variable white clip level realize wide dynamic range (140 ire) application ccd monochrome camera block diagram and pin configuration structure bipolar silicon monolithic ic absolute maximum ratings (ta = 25?) supply voltage v cc 7v storage temperature tstg ?5 to +150 ? operating temperature topr ?0 to +75 ? allowable power dissipation p d 500 mw operating conditions supply voltage v cc 4.75 to 5.25 v ?1 e89z21a78-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxA1310AQ 32 pin qfp (plastic) clp2 s/h s/h s/h s/h s/h clp2 clp1 blk clp1 blk clp1 wc agc setup blk sync drive g 2 g 1 op in op in+ det out v cc 2 video sag gnd2 pg data gnd3 iris v cc 1 gnd1 iris clp linear g out driver in wc cont set cont sync clp1 blk clp2 shp hsd2 agc max agc out g clp op out hsd1 agc cont g in 10 11 12 14 16 17 20 21 24 25 3 15 22 23 26 27 4 5 6 7 8 9 28 29 30 13 18 19 31 32 2 1 sag gnd2 gnd1 sync set cont wc cont driver in g out shp pg data shd1 shd2 op in+ op in op out agc cont v cc 1 agc max det out agc out g in g clp linear clp2 gnd3 iris iris clp blk clp1 v cc 2 video 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 32 25 26 27 28 29 30 1
?2 cxA1310AQ pin description no. symbol i/o signal 1 sag inputs video out through capacitor equivalent circuit description input pin of sag compensation signal 400a 10k 6k 150 w 1 150 w 6 wc cont gnd * 2 to 3.5v * white clip level adjusting pin preset mode control mode 150 w 40a 6 4 sync high: 4.5v and above * low: 0.5v and below t: 5s sync pulse input pin (active at low) 20a 150 w 4 2 3 gnd2 gnd1 gnd * gnd * gnd for driver and iris gnd for other than driver, sample hold and iris 5 set cont gnd * 2 to 3.5v * v cc * set-up level adjusting pin turns to preset mode 1 control mode turns to preset mode 2 40a 150 w 5 t * external applied voltage
?3 cxA1310AQ no. symbol i/o signal 7 driver in input g out through capacitor or linear equivalent circuit description input pin to driver 40a 7 10 g clp capacitor connecting pin for gamma input clamp 150 w 150 w 10 11 g in input pin of the gamma correction circuit 80a 160a 150 w 11 8 g out dc 2v gamma correction signal output pin. outputs g 1 when pin 9 is at open outputs g 2 when pin 9 is turnedto 5v 480a 8 * external applied voltage input dc permissible range dc2 to 3v * 9 linear dc 1.8v linear signal ( g -off signal) output pin pin 8 output signal turns to g 2 output 15a 150 w 480a 9 v cc *
?4 cxA1310AQ no. symbol i/o signal 12 agc out equivalent circuit description output pin of signal passed through agc 700a 12 15 v cc 1 5v * power supply for other than driver and iris 16 agc cont gain control pin of agc amplifier 16 120a 150 w 13 det out output pin of agc detection signal 320a 13 * external applied voltage 14 agc max maximum gain setting pin of agc amplifier 20a 150 w 14 vp-p max 1300mv vp-p typ 500mv dc 2.55v max 1500mv typ 500mv dc 2v dc * dc * 17 op out output pin of the operational amplifier 320a 17
?5 cxA1310AQ no. symbol i/o signal 18 op in equivalent circuit description inverted input pin of the operational amplifier 18 20a 150 w 21 shd1 input pin of the sample / hold pulse (active at high) 21 100a 150 w 19 op in+ non inverted input pin of the operational amplifier (agc detection signal input pin) 19 20a 150 w * external applied voltage 20 shd2 input pin of the sample / hold pulse (active at high) 20 100a 150 w high: 4.5v and above * low: 0.5v and below t: 15ns and above t t [ * 1 ] [ * 2 ] 22 data ccd signal input pin 150a 22 [ * 1 ] max 800mv [ * 2 ] max 800mv high: 4.5v and above * low: 0.5v and below t: 15ns and above
?6 cxA1310AQ no. symbol i/o signal 23 pg equivalent circuit description ccd single input pin 150a 23 27 iris output pin of the iris control signal 320a 27 24 shp input pin of the sample / hold pulse (active at high) 24 100a 150 w * external applied voltage 25 clp2 clp2 pulse input pin (active at high) 50a 150 w 25 high: 4.5v and above * low: 0.5v and below t: 15ns t t [ * 1 ] [ * 2 ] 28 iris clp capacitor connecting pin for iris output clamp 150 w 150 w 28 [ * 1 ] max 800mv [ * 2 ] max 800mv high: 4.5v and above * low: 0.5v and below t: 2s 26 gnd3 gnd * sample / hold gnd dc 1.3v dc13v
?7 cxA1310AQ no. symbol i/o signal equivalent circuit description 32 video video signal output pin 32 29 blk blk pulse input pin (active at low) 29 40a 150 w * external applied voltage 30 clp1 clp1 pulse input pin (active at high) 30 50a 150 w high: 4.5v and above * low: 0.5v and below t: 11s t t high: 4.5v and above * low: 0.5v and below t: 2s 31 v cc 2 5v * driver and iris power supply blk level 1.5v
?8 cxA1310AQ electrical characteristics (ta = 25?, v cc = 5v, see electrical characteristics test circuit) no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 item current consumption min. value of agc max min. value of agc cont max. value of agc cont agc cont 10db agc out dc g 1 output level g 2 output level llnear amp galn det out dc irls amp galn iris out dc drlver galn sync level setup 1 setup 2 min. value of set cont max. value of set cont w-clip level min. value of wc cont max. value of wc cont op amp output d range low level op amp output d range high level symbol lcc max ag1 ag2 ag3 adc g 1 g 2 lg ddc lg ldc dg sy se1 se2 se3 se4 wc1 wc2 wc3 opl oph conditions min. current value of v cc 1 and v cc 2 agc cont = 1.5v gain between data input and agc out data input = 100mv agc max = 4v, agc cont = 1.5v gain between data input and agc out data input = 500mv, agc cont = 5v gain between data input and agc out data input = 30mv, agc cont = 1.5v gain between data input and agc out data input = 320mv, agc cont = 3.55v dc output level of agc out test value of g 1 output level g in input = 500mv test value of g 2 output level g in input = 500mv, s9 on gain between g in input and linear g in input = 500mv dc output level of det out gain between data input and lrls data input = 300mv dc output level of iris gain between drlver ln and vldeo drlver in = 700mv sync level/dg * of video output setup level of preset mode 1 setup level/dg * of video output setup level of preset mode 2 setup level/dg * of video output setup level/dg * of video output set cont = 2v setup level/dg * of video output set cont = 3.3v w-cllp level /dg * of vldeo output drlver in = 1500mv, wc cont = gnd w-cllp level /dg * of vldeo output drlver in = 1500mv, wc cont = 2.2v w-cllp level /dg * of vldeo output drlver in = 1500mv, wc cont = 3.3v dc output level of op out op in+ = 2.5v, op ln?= 4v dc output level of op out op in+ = 4v, op ln?= 2.5v 30 30 8 2.25 530 580 1.6 1.8 8 1.1 5.7 270 ?5 0 80 780 1000 4.5 typ. 45 18 4 32 10 2.55 630 680 2.6 2.0 10 1.3 6.0 293 0 20 ? 130 820 300 1300 0.8 4.8 max. 60 20 6 12 2.85 730 780 3.6 2.2 12 1.5 6.3 316 15 40 15 860 600 1.2 unit ma db db db db v mv mv db v db v db mv mv mv mv mv mv mv mv v v * characteristics value at drlver galn item
?9 cxA1310AQ electrical characteristics test circuit 5v 0.1 0.1 5v 5v 0.01 5v s9 sag gnd2 gnd1 sync set cont wc cont driver in g out shp pg data shd1 shd2 op in+ op in op out agc cont v cc 1 agc max det out agc out g in g clp linear clp2 gnd3 iris iris clp blk clp1 v cc 2 video 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 1 31 32 25 26 27 28 29 30 20 21 (0v) (0v) 5v 0.01 0.01 (0v) (5v) v v v v a v v v a notes) 1. f is the capacitance unit of the capacitor. 2. for pins 5, 6, 14 and 16, apply voltage in brackets unless otherwise specified in the conditions column of the electrical characteristics. 3. v indicates a test pin. (test ac, dc voltage) 4. for pins 7, 11 and 22, the input signal level is at 0mv, unless otherwise specified in the conditions column of the electrical characteristics.
?10 cxA1310AQ test circuit i/o waveform diagram input level input waveform input level input level 2.4v 2.5v 2.7v 5v 0v 5s 15s 50s 5v 0v 5v 0v 2s 2s input pin output waveform output pin test test test test test test sync level 22. data 11. g in 4. sync 29. blk 30. clp1 25. clp2 7. driver in 12. agc out 8. g 1, 2 out 9. linear 13. det out 27. iris 32. video 5v 0v
?11 cxA1310AQ application circuit 5v 5v 0.01 47p 47p 0.01 10f 10f 100f 75 75 w out 0.1 47p 2200 sg 2200 47p tg iris det iris cont 2200 2200 2.2f 2.2f 5v 0.01 10f 0.01 36k 14k 5v lpf 1f 0.01 1m 10k 2700 2k 5v 1 1k 1k 100k 10k 22f 100 * 2 * 1 ccd sag gnd2 gnd1 sync set cont wc cont driver in g out shp pg data shd1 shd2 op in+ op in op out agc cont v cc 1 agc max det out agc out g in g clp linear clp2 gnd3 iris iris clp blk clp1 v cc 2 video 31 32 25 26 27 28 29 30 17 18 19 22 23 24 20 21 2 3 4 5 6 1 7 8 9 10 13 14 15 16 11 12 * 1 use a high f t transistor. (2sc3355) * 2 use a fet similar to 2sk152 or 2sk300. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?12 cxA1310AQ example of representative characteristics (vcc = 5v, ta = 25?) 40 30 20 10 0 012345 agc cont [v] gain [db] agc control characteristics 40 30 20 10 0 012345 agc max [v] gain [db] agc max control characteristics 50 0 012345 set cont [v] setup level [mv] setup control characteristics 100 preset preset 1000 800 600 400 012345 wc cont [v] white clip level [mv] white clip control characteristics preset 1000 500 0 500 1000 g in input level [mv] g 1 output level [mv] g 1 i/o characteristics 1000 500 0 500 1000 g in input level [mv] g 2 output level [mv] g 2 i/o characteristics
?13 cxA1310AQ package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 alloy 32pin qfp (plastic) 9.0 0.2 7.0 ?0.1 1.5 ?0.15 (8.0) 0.1 ?0.1 + 0.2 + 0.35 + 0.3 0.50 0.127 ?0.05 + 0.1 0?to 10 0.8 0.3 ?0.1 + 0.15 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 qfp032-p-0707 0.1

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